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https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
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initial import of rtl8812AU_8821AU_linux_v4.2.2_7502.20130517
This commit is contained in:
Anand Babu (AB) Periasamy
293
include/Hal8192DPhyCfg.h
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293
include/Hal8192DPhyCfg.h
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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/*****************************************************************************
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*
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* Module: __INC_HAL8192DPHYCFG_H
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*
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*
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* Note:
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*
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*
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* Export: Constants, macro, functions(API), global variables(None).
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
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* 2. Reorganize code architecture.
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*
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*****************************************************************************/
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/* Check to see if the file has been included already. */
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#ifndef __INC_HAL8192DPHYCFG_H
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#define __INC_HAL8192DPHYCFG_H
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 //us
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#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#ifdef CONFIG_PCI_HCI
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#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \
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{ \
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u1Byte u1bTmp; \
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u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \
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u1bTmp |= BIT0; \
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PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \
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PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \
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PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
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delay_us(100); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
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PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \
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delay_us(10); \
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PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \
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}
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#endif
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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#define CHANNEL_GROUP_MAX_2G 3
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#define CHANNEL_GROUP_IDX_5GL 3
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#define CHANNEL_GROUP_IDX_5GM 6
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#define CHANNEL_GROUP_IDX_5GH 9
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#define CHANNEL_GROUP_MAX_5G 9
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#define CHANNEL_MAX_NUMBER_2G 14
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typedef enum _MACPHY_MODE_CHANGE_ACTION{
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DMDP2DMSP = 0,
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DMSP2DMDP = 1,
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DMDP2SMSP = 2,
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SMSP2DMDP = 3,
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DMSP2SMSP = 4,
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SMSP2DMSP = 5,
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MAXACTION
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}MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
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/* BB/RF related */
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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//
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// BB and RF register read/write
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//
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void PHY_SetBBReg1Byte8192D( IN PADAPTER Adapter,
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IN u32 RegAddr,
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IN u32 BitMask,
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IN u32 Data );
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u32 PHY_QueryBBReg8192D( IN PADAPTER Adapter,
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IN u32 RegAddr,
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IN u32 BitMask );
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void PHY_SetBBReg8192D( IN PADAPTER Adapter,
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IN u32 RegAddr,
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IN u32 BitMask,
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IN u32 Data );
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u32 PHY_QueryRFReg8192D( IN PADAPTER Adapter,
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IN u8 eRFPath,
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IN u32 RegAddr,
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IN u32 BitMask );
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void PHY_SetRFReg8192D( IN PADAPTER Adapter,
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IN u8 eRFPath,
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IN u32 RegAddr,
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IN u32 BitMask,
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IN u32 Data );
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//
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// Initialization related function
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//
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/* MAC/BB/RF HAL config */
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extern int PHY_MACConfig8192D( IN PADAPTER Adapter );
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extern int PHY_BBConfig8192D( IN PADAPTER Adapter );
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extern int PHY_RFConfig8192D( IN PADAPTER Adapter );
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/* RF config */
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int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter,
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IN u8* pFileName,
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IN u8 eRFPath);
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int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter,
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IN RF_CONTENT Content,
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IN u8 eRFPath);
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/* BB/RF readback check for making sure init OK */
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int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter,
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IN HW_BLOCK_E CheckBlock,
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IN u8 eRFPath );
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/* Read initi reg value for tx power setting. */
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void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter );
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//
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// RF Power setting
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//
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//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter,
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// IN RT_RF_POWER_STATE eRFPowerState);
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//
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// BB TX Power R/W
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//
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void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter,
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OUT u32* powerlevel );
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void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter,
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IN u8 channel );
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BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter,
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IN int powerInDbm );
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//
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VOID
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PHY_ScanOperationBackup8192D(IN PADAPTER Adapter,
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IN u8 Operation );
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//
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// Switch bandwidth for 8192S
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//
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//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer );
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void PHY_SetBWMode8192D( IN PADAPTER pAdapter,
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IN CHANNEL_WIDTH ChnlWidth,
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IN unsigned char Offset );
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//
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// Set FW CMD IO for 8192S.
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//
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//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter,
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// IN IO_TYPE IOType);
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//
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// Set A2 entry to fw for 8192S
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//
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extern void FillA2Entry8192C( IN PADAPTER Adapter,
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IN u8 index,
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IN u8* val);
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//
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// channel switch related funciton
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//
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//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer );
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void PHY_SwChnl8192D( IN PADAPTER pAdapter,
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IN u8 channel );
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VOID
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PHY_SetSwChnlBWMode8192D(
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IN PADAPTER Adapter,
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IN u8 channel,
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IN CHANNEL_WIDTH Bandwidth,
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IN u8 Offset40,
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IN u8 Offset80
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);
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//
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// BB/MAC/RF other monitor API
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//
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void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter,
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IN BOOLEAN bEnableMonitorMode );
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BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter,
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IN u32 eRFPath );
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//
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// Modify the value of the hw register when beacon interval be changed.
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//
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void
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rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter,
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IN u16 BeaconInterval );
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extern VOID
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PHY_SwitchEphyParameter(
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IN PADAPTER Adapter
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);
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extern VOID
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PHY_EnableHostClkReq(
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IN PADAPTER Adapter
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);
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BOOLEAN
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SetAntennaConfig92C(
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IN PADAPTER Adapter,
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IN u8 DefaultAnt
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);
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VOID
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PHY_UpdateBBRFConfiguration8192D(
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IN PADAPTER Adapter,
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IN BOOLEAN bisBandSwitch
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);
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VOID PHY_ReadMacPhyMode92D(
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IN PADAPTER Adapter,
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IN BOOLEAN AutoloadFail
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);
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VOID PHY_ConfigMacPhyMode92D(
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IN PADAPTER Adapter
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);
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VOID PHY_ConfigMacPhyModeInfo92D(
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IN PADAPTER Adapter
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);
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VOID PHY_ConfigMacCoexist_RFPage92D(
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IN PADAPTER Adapter
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);
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VOID
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rtl8192d_PHY_InitRxSetting(
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IN PADAPTER Adapter
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);
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VOID
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rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain);
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VOID
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HalChangeCCKStatus8192D(
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IN PADAPTER Adapter,
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IN BOOLEAN bCCKDisable
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);
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VOID
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PHY_InitPABias92D(IN PADAPTER Adapter);
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/*--------------------------Exported Function prototype---------------------*/
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#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg1Byte8192D((Adapter), (RegAddr), (BitMask), (Data))
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#endif // __INC_HAL8192SPHYCFG_H
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