mirror of
https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
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initial import of rtl8812AU_8821AU_linux_v4.2.2_7502.20130517
This commit is contained in:
Anand Babu (AB) Periasamy
217
hal/OUTSRC/rtl8821a/odm_RegConfig8821A.c
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217
hal/OUTSRC/rtl8821a/odm_RegConfig8821A.c
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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//#include "Mp_Precomp.h"
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#include "../odm_precomp.h"
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#if (RTL8821A_SUPPORT == 1)
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void
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odm_ConfigRFReg_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data,
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IN ODM_RF_RADIO_PATH_E RF_PATH,
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IN u4Byte RegAddr
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)
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{
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if(Addr == 0xfe || Addr == 0xffe)
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{
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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}
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else if (Addr == 0xfd)
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{
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ODM_delay_ms(5);
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}
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else if (Addr == 0xfc)
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{
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ODM_delay_ms(1);
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}
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else if (Addr == 0xfb)
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{
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ODM_delay_us(50);
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}
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else if (Addr == 0xfa)
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{
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ODM_delay_us(5);
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}
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else if (Addr == 0xf9)
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{
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ODM_delay_us(1);
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}
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else
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{
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ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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}
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}
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void
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odm_ConfigRF_RadioA_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1000; // RF_Content: radioa_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8821A(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
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}
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// 8821 no RF B
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/*
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void
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odm_ConfigRF_RadioB_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Data
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)
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{
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u4Byte content = 0x1001; // RF_Content: radiob_txt
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u4Byte maskforPhySet= (u4Byte)(content&0xE000);
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odm_ConfigRFReg_8812A(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
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}
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*/
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void
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odm_ConfigMAC_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u1Byte Data
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)
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{
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ODM_Write1Byte(pDM_Odm, Addr, Data);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_AGC_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_PHY_REG_PG_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (Addr == 0xfd)
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ODM_delay_ms(5);
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else if (Addr == 0xfc)
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ODM_delay_ms(1);
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else if (Addr == 0xfb)
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ODM_delay_us(50);
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else if (Addr == 0xfa)
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ODM_delay_us(5);
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else if (Addr == 0xf9)
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> @@@@@@@ ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
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#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
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storePwrIndexDiffRateOffset(pDM_Odm->Adapter, Addr, Bitmask, Data);
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#endif
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}
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void
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odm_ConfigBB_PHY_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN u4Byte Addr,
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IN u4Byte Bitmask,
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IN u4Byte Data
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)
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{
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if (Addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (Addr == 0xfd)
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ODM_delay_ms(5);
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else if (Addr == 0xfc)
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ODM_delay_ms(1);
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else if (Addr == 0xfb)
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ODM_delay_us(50);
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else if (Addr == 0xfa)
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ODM_delay_us(5);
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else if (Addr == 0xf9)
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ODM_delay_us(1);
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else if (Addr == 0xa24)
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pDM_Odm->RFCalibrateInfo.RegA24 = Data;
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ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);
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// Add 1us delay between BB/RF register setting.
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ODM_delay_us(1);
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ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
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}
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void
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odm_ConfigBB_TXPWR_LMT_8821A(
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IN PDM_ODM_T pDM_Odm,
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IN pu1Byte Regulation,
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IN pu1Byte Band,
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IN pu1Byte Bandwidth,
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IN pu1Byte RateSection,
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IN pu1Byte RfPath,
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IN pu1Byte Channel,
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IN pu1Byte PowerLimit
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
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PHY_SetPowerLimitTableValue(pDM_Odm, Regulation, Band,
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Bandwidth, RateSection, RfPath, Channel, PowerLimit);
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#endif
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}
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#endif
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