mirror of
https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
synced 2025-10-20 09:31:11 +02:00
merge new version v4.3.14 from https://github.com/ptpt52/rtl8812au (#160)
This commit is contained in:
Chen Minqiang
committed by
Harshavardhana
Harshavardhana
parent
c962f7a88d
commit
00aedbde5c
@@ -1,7 +1,7 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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@@ -22,11 +22,7 @@
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//#include "hal_com.h"
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#if 1
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#include "hal_data.h"
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#else
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#include "../hal/OUTSRC/odm_precomp.h"
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#endif
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#include "rtl8192d_spec.h"
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#include "Hal8192DPhyReg.h"
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@@ -40,133 +36,133 @@
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#ifdef CONFIG_PCI_HCI
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#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
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#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
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//---------------------------------------------------------------------
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// RTL8192DE From file
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//---------------------------------------------------------------------
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#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
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#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
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#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
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#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
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#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
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#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
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//---------------------------------------------------------------------
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// RTL8192DE From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
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#elif defined(CONFIG_USB_HCI)
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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//---------------------------------------------------------------------
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// RTL8192DU From file
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//---------------------------------------------------------------------
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#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
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#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
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#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
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#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
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#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
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#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
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//---------------------------------------------------------------------
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// RTL8192DU From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
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// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
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// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
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/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
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#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
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#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
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@@ -189,7 +185,7 @@
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#endif
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//
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// Check if FW header exists. We do not consider the lower 4 bits in this case.
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// Check if FW header exists. We do not consider the lower 4 bits in this case.
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// By tynli. 2009.12.04.
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//
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#define IS_FW_HEADER_EXIST_92D(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
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@@ -205,7 +201,7 @@
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typedef struct _RT_FIRMWARE_8192D{
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typedef struct _RT_FIRMWARE_8192D {
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FIRMWARE_SOURCE eFWSource;
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u8* szFwBuffer;
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u32 ulFwLength;
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@@ -215,7 +211,7 @@ typedef struct _RT_FIRMWARE_8192D{
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// This structure must be cared byte-ordering
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//
|
||||
// Added by tynli. 2009.12.04.
|
||||
typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
|
||||
typedef struct _RT_8192D_FIRMWARE_HDR { //8-byte alinment required
|
||||
|
||||
//--- LONG WORD 0 ----
|
||||
u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
|
||||
@@ -242,18 +238,18 @@ typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
|
||||
u32 Rsvd4;
|
||||
u32 Rsvd5;
|
||||
|
||||
}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
|
||||
} RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
|
||||
|
||||
#define DRIVER_EARLY_INT_TIME_8192D 0x05
|
||||
#define BCN_DMA_ATIME_INT_TIME_8192D 0x02
|
||||
|
||||
typedef enum _BT_CurState{
|
||||
BT_OFF = 0,
|
||||
typedef enum _BT_CurState {
|
||||
BT_OFF = 0,
|
||||
BT_ON = 1,
|
||||
} BT_CurState, *PBT_CurState;
|
||||
|
||||
typedef enum _BT_ServiceType{
|
||||
BT_SCO = 0,
|
||||
typedef enum _BT_ServiceType {
|
||||
BT_SCO = 0,
|
||||
BT_A2DP = 1,
|
||||
BT_HID = 2,
|
||||
BT_HID_Idle = 3,
|
||||
@@ -264,7 +260,7 @@ typedef enum _BT_ServiceType{
|
||||
BT_OtherBusy = 8,
|
||||
} BT_ServiceType, *PBT_ServiceType;
|
||||
|
||||
typedef struct _BT_COEXIST_STR{
|
||||
typedef struct _BT_COEXIST_STR {
|
||||
u8 BluetoothCoexist;
|
||||
u8 BT_Ant_Num;
|
||||
u8 BT_CoexistType;
|
||||
@@ -272,11 +268,11 @@ typedef struct _BT_COEXIST_STR{
|
||||
u8 BT_CUR_State; //0:on, 1:off
|
||||
u8 BT_Ant_isolation; //0:good, 1:bad
|
||||
u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
|
||||
u8 BT_Service;
|
||||
u8 BT_Service;
|
||||
u8 BT_RadioSharedType;
|
||||
u8 Ratio_Tx;
|
||||
u8 Ratio_PRI;
|
||||
}BT_COEXIST_STR, *PBT_COEXIST_STR;
|
||||
} BT_COEXIST_STR, *PBT_COEXIST_STR;
|
||||
|
||||
|
||||
|
||||
@@ -353,7 +349,7 @@ typedef struct _BT_COEXIST_STR{
|
||||
typedef enum _PA_MODE {
|
||||
PA_MODE_EXTERNAL = 0x00,
|
||||
PA_MODE_INTERNAL_SP3T = 0x01,
|
||||
PA_MODE_INTERNAL_SPDT = 0x02
|
||||
PA_MODE_INTERNAL_SPDT = 0x02
|
||||
} PA_MODE;
|
||||
|
||||
/* Copy from rtl8192c */
|
||||
@@ -390,9 +386,6 @@ void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
|
||||
VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
|
||||
#endif
|
||||
|
||||
|
||||
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
|
||||
|
||||
int FirmwareDownload92D(IN PADAPTER Adapter);
|
||||
VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
|
||||
void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
|
||||
@@ -404,7 +397,10 @@ BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
|
||||
VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
|
||||
//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
|
||||
void rtl8192d_free_hal_data(_adapter * padapter);
|
||||
void rtl8192d_init_default_value(_adapter *adapter);
|
||||
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
|
||||
void rtl8192d_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
|
||||
|
||||
void SetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
|
||||
void GetHwReg8192D(_adapter *adapter, u8 variable, u8 *val);
|
||||
#endif
|
||||
|
||||
|
||||
Reference in New Issue
Block a user