mirror of
https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
synced 2025-10-19 09:01:10 +02:00
merge new version v4.3.14 from https://github.com/ptpt52/rtl8812au (#160)
This commit is contained in:
Chen Minqiang
committed by
Harshavardhana
Harshavardhana
parent
c962f7a88d
commit
00aedbde5c
@@ -26,9 +26,9 @@
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//====================================================
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#define EEPROM_VID_92C 0x0A
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#define EEPROM_PID_92C 0x0C
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#define EEPROM_DID_92C 0x0C
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#define EEPROM_DID_92C 0x0C
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#define EEPROM_SVID_92C 0x0E
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#define EEPROM_SMID_92C 0x10
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#define EEPROM_SMID_92C 0x10
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#define EEPROM_MAC_ADDR_92C 0x16
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#define EEPROM_MAC_ADDR 0x16
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@@ -58,6 +58,10 @@
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#define BOARD_TYPE_TEST_MASK 0xF
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#define EEPROM_TYPE_ID 0x7E
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// PCIe related
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#define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74
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#define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75
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// EEPROM address for Test chip
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#define EEPROM_TEST_USB_OPT 0x0E
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@@ -70,8 +74,8 @@
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#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16
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#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C
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#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F
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#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
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#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
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#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
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#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
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#define EEPROM_ChannelPlan_8723A 0x28
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#define EEPROM_TSSI_A_8723A 0x29
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@@ -158,7 +162,7 @@
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#define EEPROM_HT20_MAX_PWR_OFFSET_5GH_92D 0xB8
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#define EEPROM_CHANNEL_PLAN_92D 0xBB // Map of supported channels.
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#define EEPROM_CHANNEL_PLAN_92D 0xBB // Map of supported channels.
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#define EEPROM_TEST_CHANNEL_PLAN_92D 0xBB
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#define EEPROM_THERMAL_METER_92D 0xC3 //[4:0]
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#define EEPROM_IQK_DELTA_92D 0xBC
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@@ -232,7 +236,8 @@
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#define EEPROM_MAC_ADDR_88EU 0xD7
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#define EEPROM_VID_88EU 0xD0
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#define EEPROM_PID_88EU 0xD2
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#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4
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#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8192EU, 8812AU is the same
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#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
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// RTL88ES
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#define EEPROM_MAC_ADDR_88ES 0x11A
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@@ -276,7 +281,7 @@
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#define EEPROM_LNA_TYPE_5G_8192EU 0xBF
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// RTL8192ES
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#define EEPROM_MAC_ADDR_8192ES 0x11B
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#define EEPROM_MAC_ADDR_8192ES 0x11A
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//====================================================
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// EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
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//====================================================
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@@ -373,11 +378,11 @@
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#define EEPROM_VID_92SU 0x08
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#define EEPROM_PID_92SU 0x0A
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#define EEPROM_PID_92SU 0x0A
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#define EEPROM_Version_92SU 0x50
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#define EEPROM_TSSI_A_92SU 0x6b
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#define EEPROM_TSSI_B_92SU 0x6c
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#define EEPROM_TSSI_A_92SU 0x6b
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#define EEPROM_TSSI_B_92SU 0x6c
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//====================================================
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// EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
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@@ -411,14 +416,15 @@
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#define EEPROM_SMID_8723BE 0xDC
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//RTL8723BU
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#define EEPROM_MAC_ADDR_8723BU 0xD7
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#define EEPROM_VID_8723BU 0xD0
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#define EEPROM_PID_8723BU 0xD2
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#define EEPROM_MAC_ADDR_8723BU 0x107
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#define EEPROM_VID_8723BU 0x100
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#define EEPROM_PID_8723BU 0x102
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#define EEPROM_PA_TYPE_8723BU 0xBC
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#define EEPROM_LNA_TYPE_2G_8723BU 0xBD
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//RTL8723BS
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#define EEPROM_MAC_ADDR_8723BS 0x11A
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#define EEPROM_Voltage_ADDR_8723B 0x8
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//====================================================
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@@ -486,7 +492,7 @@
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#define EEPROM_Default_HT20_Diff 2
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#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
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#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3
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#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4
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#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4
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#define EEPROM_Default_HT40_PwrMaxOffset 0
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#define EEPROM_Default_HT20_PwrMaxOffset 0
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@@ -511,9 +517,9 @@
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#define EEPROM_Default_LNAType 0
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//New EFUSE deafult value
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#define EEPROM_DEFAULT_24G_INDEX 0x2A
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#define EEPROM_DEFAULT_24G_INDEX 0x2D
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#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02
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#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04
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#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04
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#define EEPROM_DEFAULT_5G_INDEX 0X2A
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#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00
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@@ -531,21 +537,23 @@
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//
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// For VHT series TX power by rate table.
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// VHT TX power by rate off setArray =
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// VHT TX power by rate off setArray =
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// Band:-2G&5G = 0 / 1
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// RF: at most 4*4 = ABCD=0/1/2/3
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// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
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// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
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//
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#define TX_PWR_BY_RATE_NUM_BAND 2
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#define TX_PWR_BY_RATE_NUM_RF 4
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#define TX_PWR_BY_RATE_NUM_SECTION 12
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#define TX_PWR_BY_RATE_NUM_RATE 84
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#define TXPWR_LMT_MAX_RF 4
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//----------------------------------------------------------------------------
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// EEPROM/EFUSE data structure definition.
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//----------------------------------------------------------------------------
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#define MAX_RF_PATH_NUM 2
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#define MAX_CHNL_GROUP 3+9
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typedef struct _TxPowerInfo{
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typedef struct _TxPowerInfo {
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u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
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u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
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u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
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@@ -557,13 +565,13 @@ typedef struct _TxPowerInfo{
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u8 TSSI_B[3];
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u8 TSSI_A_5G[3]; //5GL/5GM/5GH
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u8 TSSI_B_5G[3];
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}TxPowerInfo, *PTxPowerInfo;
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} TxPowerInfo, *PTxPowerInfo;
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//For 88E new structure
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/*
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2.4G:
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2.4G:
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{
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{1,2},
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{3,4,5},
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@@ -591,24 +599,24 @@ typedef struct _TxPowerInfo{
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}
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*/
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#define MAX_RF_PATH 4
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#define RF_PATH_MAX MAX_RF_PATH
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#define MAX_CHNL_GROUP_24G 6
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#define MAX_CHNL_GROUP_5G 14
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#define RF_PATH_MAX MAX_RF_PATH
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#define MAX_CHNL_GROUP_24G 6
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#define MAX_CHNL_GROUP_5G 14
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//It must always set to 4, otherwise read efuse table secquence will be wrong.
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#define MAX_TX_COUNT 4
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typedef struct _TxPowerInfo24G{
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typedef struct _TxPowerInfo24G {
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u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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//If only one tx, only BW20 and OFDM are used.
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s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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}TxPowerInfo24G, *PTxPowerInfo24G;
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} TxPowerInfo24G, *PTxPowerInfo24G;
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typedef struct _TxPowerInfo5G{
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typedef struct _TxPowerInfo5G {
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u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
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//If only one tx, only BW20, OFDM, BW80 and BW160 are used.
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s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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@@ -616,17 +624,17 @@ typedef struct _TxPowerInfo5G{
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s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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}TxPowerInfo5G, *PTxPowerInfo5G;
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} TxPowerInfo5G, *PTxPowerInfo5G;
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typedef enum _BT_Ant_NUM{
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Ant_x2 = 0,
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typedef enum _BT_Ant_NUM {
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Ant_x2 = 0,
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Ant_x1 = 1
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} BT_Ant_NUM, *PBT_Ant_NUM;
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typedef enum _BT_CoType{
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BT_2Wire = 0,
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BT_ISSC_3Wire = 1,
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typedef enum _BT_CoType {
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BT_2WIRE = 0,
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BT_ISSC_3WIRE = 1,
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BT_ACCEL = 2,
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BT_CSR_BC4 = 3,
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BT_CSR_BC8 = 4,
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@@ -634,10 +642,13 @@ typedef enum _BT_CoType{
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BT_RTL8723A = 6,
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BT_RTL8821 = 7,
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BT_RTL8723B = 8,
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BT_RTL8192E = 9,
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BT_RTL8813A = 10,
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BT_RTL8812A = 11
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} BT_CoType, *PBT_CoType;
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typedef enum _BT_RadioShared{
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BT_Radio_Shared = 0,
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typedef enum _BT_RadioShared {
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BT_Radio_Shared = 0,
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BT_Radio_Individual = 1,
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} BT_RadioShared, *PBT_RadioShared;
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