mirror of
https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
synced 2025-10-19 09:01:10 +02:00
merge new version v4.3.14 from https://github.com/ptpt52/rtl8812au (#160)
This commit is contained in:
Chen Minqiang
committed by
Harshavardhana
Harshavardhana
parent
c962f7a88d
commit
00aedbde5c
@@ -33,11 +33,13 @@
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// BB Register Definition
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#define rCCAonSec_Jaguar 0x838
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#define rPwed_TH_Jaguar 0x830
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// BW and sideband setting
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#define rBWIndication_Jaguar 0x834
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#define rL1PeakTH_Jaguar 0x848
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#define rRFMOD_Jaguar 0x8ac //RF mode
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#define rL1PeakTH_Jaguar 0x848
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#define rFPGA0_XA_LSSIReadBack 0x8a0 /*Tranceiver LSSI Readback*/
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#define rRFMOD_Jaguar 0x8ac //RF mode
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#define rADC_Buf_Clk_Jaguar 0x8c4
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#define rRFECTRL_Jaguar 0x900
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#define bRFMOD_Jaguar 0xc3
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@@ -53,7 +55,7 @@
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#define rTxPath_Jaguar 0x80c // Tx antenna
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#define bTxPath_Jaguar 0x0fffffff
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#define rCCK_RX_Jaguar 0xa04 // for cck rx path selection
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#define bCCK_RX_Jaguar 0x0c000000
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#define bCCK_RX_Jaguar 0x0c000000
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#define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length
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// RF read/write-related
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@@ -72,7 +74,7 @@
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// YN: mask the following register definition temporarily
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// YN: mask the following register definition temporarily
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#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
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#define rFPGA0_XB_RFInterfaceOE 0x864
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@@ -104,7 +106,7 @@
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// YN: mask the following register definition temporarily
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//#define rPdp_AntA 0xb00
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//#define rPdp_AntA 0xb00
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//#define rPdp_AntA_4 0xb04
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//#define rConfig_Pmpd_AntA 0xb28
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//#define rConfig_AntA 0xb68
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@@ -140,7 +142,7 @@
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#define rB_TxPwrTraing_Jaguar 0xe54
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// Report-related
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#define rOFDM_ShortCFOAB_Jaguar 0xf60
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#define rOFDM_ShortCFOAB_Jaguar 0xf60
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#define rOFDM_LongCFOAB_Jaguar 0xf64
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#define rOFDM_EndCFOAB_Jaguar 0xf70
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#define rOFDM_AGCReport_Jaguar 0xf84
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@@ -155,22 +157,22 @@
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#define bAGC_table_Jaguar 0x3
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#define b_sel5g_Jaguar 0x1000 // sel5g
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#define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA
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#define rFc_area_Jaguar 0x860 // fc_area
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#define rFc_area_Jaguar 0x860 // fc_area
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#define bFc_area_Jaguar 0x1ffe000
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#define rSingleTone_ContTx_Jaguar 0x914
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// RFE
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#define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux
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#define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux
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#define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol
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#define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol
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#define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control
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#define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol
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#define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol
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#define rB_RFE_Jaguar 0xeb8 // Path_B RFE control
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#define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control
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#define bMask_RFEInv_Jaguar 0x3ff00000
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#define bMask_AntselPathFollow_Jaguar 0x00030000
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// TX AGC
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// TX AGC
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#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
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#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
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#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
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@@ -262,42 +264,47 @@
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// RSSI Dump
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#define rA_RSSIDump_Jaguar 0xBF0
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#define rB_RSSIDump_Jaguar 0xBF1
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#define rS1_RXevmDump_Jaguar 0xBF4
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#define rS1_RXevmDump_Jaguar 0xBF4
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#define rS2_RXevmDump_Jaguar 0xBF5
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#define rA_RXsnrDump_Jaguar 0xBF6
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#define rB_RXsnrDump_Jaguar 0xBF7
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#define rA_CfoShortDump_Jaguar 0xBF8
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#define rA_CfoShortDump_Jaguar 0xBF8
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#define rB_CfoShortDump_Jaguar 0xBFA
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#define rA_CfoLongDump_Jaguar 0xBEC
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#define rB_CfoLongDump_Jaguar 0xBEE
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// RF Register
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//
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#define RF_AC_Jaguar 0x00 //
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#define RF_RF_Top_Jaguar 0x07 //
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#define RF_TXLOK_Jaguar 0x08 //
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#define RF_AC_Jaguar 0x00 //
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#define RF_RF_Top_Jaguar 0x07 //
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#define RF_TXLOK_Jaguar 0x08 //
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#define RF_TXAPK_Jaguar 0x0B
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#define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch
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#define RF_TxLCTank_Jaguar 0x54
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#define RF_APK_Jaguar 0x63
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#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
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#define bRF_CHNLBW_BW 0xc00
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#define RF_RCK1_Jaguar 0x1c //
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#define RF_RCK1_Jaguar 0x1c //
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#define RF_RCK2_Jaguar 0x1d
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#define RF_RCK3_Jaguar 0x1e
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#define RF_ModeTableAddr 0x30
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#define RF_ModeTableData0 0x31
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#define RF_ModeTableData1 0x32
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#define RF_TxLCTank_Jaguar 0x54
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#define RF_APK_Jaguar 0x63
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#define RF_LCK 0xB4
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#define RF_WeLut_Jaguar 0xEF
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#define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
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#define bRF_CHNLBW_BW 0xc00
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//
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// RL6052 Register definition
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//
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#define RF_AC 0x00 //
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#define RF_IPA_A 0x0C //
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#define RF_AC 0x00 //
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#define RF_IPA_A 0x0C //
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#define RF_TXBIAS_A 0x0D
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#define RF_BS_PA_APSET_G9_G11 0x0E
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#define RF_MODE1 0x10 //
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#define RF_MODE2 0x11 //
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#define RF_MODE1 0x10 //
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#define RF_MODE2 0x11 //
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#define RF_CHNLBW 0x18 // RF channel and BW switch
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#define RF_RCK_OS 0x30 // RF TX PA control
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#define RF_TXPA_G1 0x31 // RF TX PA control
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@@ -414,6 +421,8 @@
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#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
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#define rFPGA0_AnalogParameter4 0x88c
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#define rFPGA0_XB_LSSIReadBack 0x8a4
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#define rFPGA0_XCD_RFPara 0x8b4
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//
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// 4. Page9(0x900)
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//
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@@ -428,14 +437,16 @@
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//
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#define rCCK0_System 0xa00
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#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
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#define rCCK0_DSPParameter2 0xa1c //SQ threshold
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#define rCCK0_TxFilter1 0xa20
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#define rCCK0_TxFilter2 0xa24
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#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
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#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
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//
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// PageB(0xB00)
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//
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#define rPdp_AntA 0xb00
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#define rPdp_AntA 0xb00
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#define rPdp_AntA_4 0xb04
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#define rConfig_Pmpd_AntA 0xb28
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#define rConfig_AntA 0xb68
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@@ -464,7 +475,7 @@
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#define rOFDM0_XDRxIQImbalance 0xc2c
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#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
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#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
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#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
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#define rOFDM0_RxDetector3 0xc38 //Frame Sync.
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#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
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@@ -668,9 +679,9 @@
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#define bCCKRxFACounterLower 0xff
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#define bCCKRxFACounterUpper 0xff000000
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#define bCCKRxHPAGCStart 0xe000
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#define bCCKRxHPAGCFinal 0x1c00
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#define bCCKRxHPAGCFinal 0x1c00
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#define bCCKRxFalseAlarmEnable 0x8000
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#define bCCKFACounterFreeze 0x4000
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#define bCCKFACounterFreeze 0x4000
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#define bCCKTxPathSel 0x10000000
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#define bCCKDefaultRxPath 0xc000000
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#define bCCKOptionRxPath 0x3000000
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@@ -711,8 +722,9 @@
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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#define bMask12Bits 0xfff
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#define bMaskH4Bits 0xf0000000
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#define bMaskH3Bytes 0xffffff00
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#define bMask12Bits 0xfff
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#define bMaskH4Bits 0xf0000000
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#define bMaskOFDM_D 0xffc00000
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#define bMaskCCK 0x3f3f3f3f
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