mirror of
https://github.com/abperiasamy/rtl8812AU_8821AU_linux.git
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merge new version v4.3.14 from https://github.com/ptpt52/rtl8812au (#160)
This commit is contained in:
Chen Minqiang
committed by
Harshavardhana
Harshavardhana
parent
c962f7a88d
commit
00aedbde5c
@@ -46,11 +46,11 @@ Major Change History:
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// 2011.07.07, added by Roger.
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//
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u8 HalPwrSeqCmdParsing(
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PADAPTER padapter,
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u8 CutVersion,
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u8 FabVersion,
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u8 InterfaceType,
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WLAN_PWR_CFG PwrSeqCmd[])
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PADAPTER padapter,
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u8 CutVersion,
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u8 FabVersion,
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u8 InterfaceType,
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WLAN_PWR_CFG PwrSeqCmd[])
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{
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WLAN_PWR_CFG PwrCfgCmd = {0};
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u8 bPollingBit = _FALSE;
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@@ -64,118 +64,114 @@ u8 HalPwrSeqCmdParsing(
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PwrCfgCmd = PwrSeqCmd[AryIdx];
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RT_TRACE(_module_hal_init_c_ , _drv_info_,
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("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
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GET_PWR_CFG_OFFSET(PwrCfgCmd),
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GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
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GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
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GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
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GET_PWR_CFG_BASE(PwrCfgCmd),
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GET_PWR_CFG_CMD(PwrCfgCmd),
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GET_PWR_CFG_MASK(PwrCfgCmd),
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GET_PWR_CFG_VALUE(PwrCfgCmd)));
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("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n",
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GET_PWR_CFG_OFFSET(PwrCfgCmd),
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GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
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GET_PWR_CFG_FAB_MASK(PwrCfgCmd),
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GET_PWR_CFG_INTF_MASK(PwrCfgCmd),
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GET_PWR_CFG_BASE(PwrCfgCmd),
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GET_PWR_CFG_CMD(PwrCfgCmd),
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GET_PWR_CFG_MASK(PwrCfgCmd),
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GET_PWR_CFG_VALUE(PwrCfgCmd)));
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//2 Only Handle the command whose FAB, CUT, and Interface are matched
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if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) &&
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(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
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(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType))
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{
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switch (GET_PWR_CFG_CMD(PwrCfgCmd))
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{
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case PWR_CMD_READ:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
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break;
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(GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) &&
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(GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) {
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switch (GET_PWR_CFG_CMD(PwrCfgCmd)) {
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case PWR_CMD_READ:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n"));
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break;
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case PWR_CMD_WRITE:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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case PWR_CMD_WRITE:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n"));
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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#ifdef CONFIG_SDIO_HCI
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//
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// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
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// 2011.07.07.
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//
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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{
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// Read Back SDIO Local value
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value = SdioLocalCmd52Read1Byte(padapter, offset);
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//
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// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
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// 2011.07.07.
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//
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) {
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// Read Back SDIO Local value
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value = SdioLocalCmd52Read1Byte(padapter, offset);
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value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
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value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
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value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
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value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
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// Write Back SDIO Local value
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SdioLocalCmd52Write1Byte(padapter, offset, value);
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}
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else
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// Write Back SDIO Local value
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SdioLocalCmd52Write1Byte(padapter, offset, value);
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} else
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#endif
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{
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#ifdef CONFIG_GSPI_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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offset = SPI_LOCAL_OFFSET | offset;
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#endif
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// Read the value from system register
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value = rtw_read8(padapter, offset);
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value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
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value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
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// Write the value back to sytem register
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rtw_write8(padapter, offset, value);
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}
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break;
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case PWR_CMD_POLLING:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
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bPollingBit = _FALSE;
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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{
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#ifdef CONFIG_GSPI_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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offset = SPI_LOCAL_OFFSET | offset;
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#endif
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do {
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#ifdef CONFIG_SDIO_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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value = SdioLocalCmd52Read1Byte(padapter, offset);
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else
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// Read the value from system register
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value = rtw_read8(padapter, offset);
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value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
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value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
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// Write the value back to sytem register
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rtw_write8(padapter, offset, value);
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}
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break;
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case PWR_CMD_POLLING:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n"));
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bPollingBit = _FALSE;
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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#ifdef CONFIG_GSPI_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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offset = SPI_LOCAL_OFFSET | offset;
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#endif
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value = rtw_read8(padapter, offset);
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value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
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if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
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bPollingBit = _TRUE;
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else
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rtw_udelay_os(10);
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if (pollingCount++ > maxPollingCnt) {
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DBG_871X("Fail to polling Offset[%#x]\n", offset);
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return _FALSE;
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}
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} while (!bPollingBit);
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break;
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case PWR_CMD_DELAY:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
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if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
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rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
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do {
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#ifdef CONFIG_SDIO_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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value = SdioLocalCmd52Read1Byte(padapter, offset);
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else
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rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
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break;
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#endif
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value = rtw_read8(padapter, offset);
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case PWR_CMD_END:
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// When this command is parsed, end the process
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
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return _TRUE;
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break;
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value=value&GET_PWR_CFG_MASK(PwrCfgCmd);
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if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)))
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bPollingBit = _TRUE;
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else
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rtw_udelay_os(10);
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default:
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RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
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break;
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if (pollingCount++ > maxPollingCnt) {
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DBG_871X_LEVEL(_drv_always_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value);
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return _FALSE;
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}
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} while (!bPollingBit);
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break;
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case PWR_CMD_DELAY:
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n"));
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if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
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rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd));
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else
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rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
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break;
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case PWR_CMD_END:
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// When this command is parsed, end the process
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RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n"));
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return _TRUE;
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break;
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default:
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RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n"));
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break;
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}
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}
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AryIdx++;//Add Array Index
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}while(1);
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} while(1);
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return _TRUE;
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}
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